As an important part of the semiconductor integrated circuit industry, the contact holes filled by tungsten and then processed by chemical mechanical planarization (CMP) can make a significant effect directly on the resistance-capacitance (RC) of the whole device.
As the sizes of devices become smaller, and the TiN film and the Ti barrier layer between tungsten and the dielectric layer are thinner, it becomes more difficult to control the CMP technology. In this case over-grinding is common which results in significant fluctuations in the thickness of the dielectric layer, and this reduces the stability of the devices and the yield of products.
In 65 nanometer technology, as the sizes of the devices become smaller, amorphous carbon is typically used in the contact holes as a hard mask when etching. It is common to remove the amorphous carbon after finishing the etching, and then subsequent processes can be started. Because the hardness of the amorphous carbon is extremely high, it can be a good stop layer for use with the CMP technology.